The invention relates generally to integrated circuits and more particularly to the use of platinum-rhodium (Ptxe2x80x94Rh) alloy materials for electrodes and diffusion barrier layers to protect cell dielectrics in such circuits. The invention further relates generally to the preparation of rhodium-containing layers on substrates, particularly on semiconductor device structures.
Layers of metals and metal oxides, particularly the heavier elements of Group VIII, are becoming important for a variety of electronic and electrochemical applications. For example, high quality RuO2 thin films deposited on silicon wafers have recently gained interest for use in ferroelectric memories. Many of the Group VIII metal layers are generally unreactive toward silicon and metal oxides, resistant to diffusion of oxygen and silicon, and are good conductors. Oxides of certain of these metals also possess these properties, although perhaps to a different extent.
Thus, layers of Group VIII metals and metal oxides, particularly the second and third row metals (e.g., Ru, Os, Rh, Ir, Pd, and Pt) have suitable properties for a variety of uses in integrated circuits. For example, they can be used in integrated circuits for electrical contacts. They are particularly suitable for use as barrier layers between the dielectric material and the silicon substrate in memory devices, such as ferroelectric memories. Furthermore, they may even be suitable as the plate (i.e., electrode) itself in capacitors. Rhodium is of particular interest because it is one of a few elements having a resistivity of less than 5 xcexcxcexa9-cm (resistivity at 20xc2x0 C.=4.51 xcexcxcexa9-cm).
Capacitors are used in a wide variety of integrated circuits. Capacitors are of special concern in DRAM (dynamic random access memory) circuits; therefore, the invention will be discussed in connection with DRAM memory circuits. However, the invention has broader applicability and is not limited to DRAM memory circuits. It may be used in other types of memory circuits, such as SRAMs, as well as any other circuit in which cell dielectrics are used.
There is continuous pressure in the industry to decrease the size of individual cells and increase memory cell density to allow more memory to be squeezed onto a single memory chip. However, it is necessary to maintain a sufficiently high storage capacitance to maintain a charge at the refresh rates currently in use even as cell size continues to shrink. This requirement has led DRAM manufacturers to turn to three dimensional capacitor designs, including trench and stacked capacitors. Stacked capacitors are capacitors which are formed over the access transistor in a semiconductor device. In contrast, trench capacitors are formed in the wafer substrate beneath the transistor. For reasons including ease of fabrication and increased capacitance, most manufacturers of DRAMs larger than 4 Megabits use stacked capacitors. Therefore, the present invention will be discussed in connection with stacked capacitors, but should not be understood to be limited thereto.
One widely used type of stacked capacitor is known as a container capacitor. Known container capacitors are in the shape of an upstanding tube (cylinder) with an oval or circular cross section. The wall of the tube consists of two electrodes, i.e., two plates of conductive material, such as doped polycrystalline silicon (referred to herein as polysilicon or poly), separated by a dielectric, such as tantalum pentoxide (Ta2O5). The bottom end of the tube is closed, with the outer wall in contact with either the drain of the access transistor or a plug which itself is in contact with the drain. The other end of the tube is open. The sidewall and closed end of the tube form a container; hence the name xe2x80x9ccontainer capacitor.xe2x80x9d
The electrodes in a DRAM cell capacitor must protect the dielectric layer from interaction with surrounding materials, including interlayer dielectrics (e.g., BPSG), and from the harsh thermal processing encountered in subsequent steps of DRAM process flow. In order to function well as a bottom electrode, the electrode layer or layer stack must act as an effective barrier to the diffusion of oxygen and silicon. Oxidation of the underlying Si will result in decreased series capacitance, thus degrading the cell capacitor. Platinum is one of the candidates for use as an electrode material for high dielectric capacitors. Platinum, alone, however, is relatively permeable to oxygen. One solution is to alloy the Pt with Rh to enhance the barrier properties of the layer. Physical vapor deposition (PVD) of a Ptxe2x80x94Rh alloy has been shown by H. D. Bhatt et. al., xe2x80x9cNovel high temperature multi-layer electrode barrier structure for high-density ferroelectric memories,xe2x80x9d Applied Physics Letters, 71, pp. 719-21 (1997), to provide an improvement over pure Pt for electrode applications. However, PVD deposition does not deliver a layer which is sufficiently conformal for VLSI devices.
Thus, there is a continuing need for methods and materials for the deposition of metal-containing layers, such as rhodium-containing layers, which can function as barrier layers, for example, in integrated circuits. Furthermore, what is needed are capacitor electrodes, barrier layers, and fabrication methods that offer a combination of good conformality, high conductivity, and good barrier properties.
The present invention is directed to methods for manufacturing a semiconductor device that involve forming a rhodium-containing layer on substrates, such as semiconductor substrates or substrate assemblies during the manufacture of semiconductor structures. The rhodium-containing layer can be a pure rhodium layer, a rhodium oxide layer, a rhodium sulfide layer, a rhodium selenide layer, a rhodium nitride layer, a rhodium alloy layer, or the like. Typically and preferably, the rhodium-containing layer is electrically conductive. The resultant layer can be used as a barrier layer or electrode in an integrated circuit structure, particularly in a memory device such as a DRAM device.
The metal-containing layer can include pure rhodium, or a rhodium alloy containing rhodium and one or more other metals (including transition metals, main group metals, lanthanides) or metalloids from other groups in the Periodic Chart, such as Si, Ge, Sn, Pb, Bi, etc. Furthermore, for certain preferred embodiments, the metal-containing layer can be an oxide, nitride, sulfide, selenide, telluride, or combinations thereof.
Thus, in the context of the present invention, the term xe2x80x9cmetal-containing layerxe2x80x9d includes, for example, relatively pure layers of rhodium, alloys of rhodium with other Group VIII transition metals such as iridium, nickel, palladium, platinum, iron, ruthenium, and osmium, metals other than those in Group VIII, metalloids (e.g., Si), or mixtures thereof. The term also includes complexes of rhodium or rhodium alloys with other elements (e.g., O, N, and S). The terms xe2x80x9csingle transition metal layerxe2x80x9d or xe2x80x9csingle metal layerxe2x80x9d refer to relatively pure layers of rhodium. The terms xe2x80x9ctransition metal alloy layerxe2x80x9d or xe2x80x9cmetal alloy layerxe2x80x9d refer to layers of rhodium in alloys with other metals or metalloids, for example.
One preferred method of the present invention involves forming a layer on a substrate, such as a semiconductor substrate or substrate assembly during the manufacture of a semiconductor structure. The method includes: providing a substrate (preferably, a semiconductor substrate or substrate assembly); providing a precursor composition comprising one or more complexes of the formula:
LyRhYz,xe2x80x83xe2x80x83(Formula I)
wherein: each L group is independently a neutral or anionic ligand; each Y group is independently a pi bonding ligand selected from the group of CO, NO, CN, CS, N2, PX3, PR3, P(OR)3, AsX3, AsR3, As(OR)3, SbX3, SbR3, Sb(OR)3, NHxR3xe2x88x92x, CNR, and RCN, wherein R is an organic group and X is a halide; y=1 to 4; z=0 to 4 (preferably, 1 to 4); x=0 to 3; providing a nonhydrogen reaction gas; and forming a metal-containing layer from the precursor composition in the presence of the nonhydrogen reaction gas on a surface of the substrate (preferably, the semiconductor substrate or substrate assembly). The metal-containing layer can be a single transition metal layer or a transition metal alloy layer, for example. Using such methods, the complexes of Formula I are converted in some manner (e.g., decomposed thermally) and deposited on a surface to form a metal-containing layer. Thus, the layer is not simply a layer of the complex of Formula I.
Complexes of Formula I are neutral complexes and may be liquids or solids at room temperature. Typically, however, they are liquids. If they are solids, they are preferably sufficiently soluble in an organic solvent or have melting points below their decomposition temperatures such that they can be used in various vaporization techniques, such as flash vaporization, bubbling, microdroplet formation, etc. However, they may also be sufficiently volatile that they can be vaporized or sublimed from the solid state using known chemical vapor deposition techniques. Thus, the precursor compositions of the present invention can be in solid or liquid form. As used herein, xe2x80x9cliquidxe2x80x9d refers to a solution or a neat liquid (a liquid at room temperature or a solid at room temperature that melts at an elevated temperature). As used herein, a xe2x80x9csolutionxe2x80x9d does not require complete solubility of the solid; rather, the solution may have some undissolved material, preferably, however, there is a sufficient amount of the material that can be carried by the organic solvent into the vapor phase for chemical vapor deposition processing.
Yet another method of forming a metal-containing layer on a substrate, such as a semiconductor substrate or substrate assembly during the manufacture of a semiconductor structure, involves: providing a substrate (preferably, a semiconductor substrate or substrate assembly); providing a precursor composition comprising one or more organic solvents and one or more precursor complexes of Formula I as defined above; providing a nonhydrogen reaction gas, preferably an oxidizing gas; vaporizing the precursor composition to form vaporized precursor composition; and directing the vaporized precursor composition toward the substrate to form a metal-containing layer in the presence of a nonhydrogen reaction as on a surface of the substrate. Herein, vaporized precursor composition includes vaporized molecules of precursor complexes of Formula I either alone or optionally with vaporized molecules of other compounds in the precursor composition, including solvent molecules, if used.
Still another method of forming a layer on a substrate involves: providing a substrate; providing a precursor composition comprising one or more complexes of Formula I with the proviso that L is not cyclopentadienyl when Y is CO (particularly, if a hydrogen reaction gas is provided); and forming a rhodium-containing layer from the precursor composition on a surface of the substrate.
Preferred embodiments of the methods of the present invention involve the use of one or more chemical vapor deposition techniques, although this is not necessarily required. That is, for certain embodiments, spin-on coating, dip coating, etc., can be used.
Methods of the present invention are particularly well suited for forming layers on a surface of a semiconductor substrate or substrate assembly, such as a silicon wafer, with or without layers or structures formed thereon, used in forming integrated circuits. It is to be understood that methods of the present invention are not limited to deposition on silicon wafers; rather, other types of wafers (e.g., gallium arsenide wafers, etc.) can be used as well. Also, for certain embodiments the methods of the present invention can be used in silicon-on-insulator technology. Furthermore, substrates other than semiconductor substrates or substrate assemblies can be used in methods of the present invention. These include, for example, fibers, wires, etc. If the substrate is a semiconductor substrate or substrate assembly, the layers can be formed directly on the lowest semiconductor surface of the substrate, or they can be formed on any of a variety of the layers (i.e., surfaces) as in a patterned wafer, for example. Thus, the term xe2x80x9csemiconductor substratexe2x80x9d refers to the base semiconductor layer, e.g., the lowest layer of silicon material in a wafer or a silicon layer deposited on another material such as silicon on sapphire. The term xe2x80x9csemiconductor substrate assemblyxe2x80x9d refers to the semiconductor substrate having one or more layers or structures formed thereon.
A chemical vapor deposition system is also provided. The system includes a deposition chamber having a substrate positioned therein; a vessel containing a precursor composition comprising one or more complexes of Formula I as described above; a source of an inert carrier gas for transferring the precursor composition to the chemical vapor deposition chamber; and a source of a nonhydrogen reaction gas.
The present invention also provides platinum-rhodium (Ptxe2x80x94Rh) alloy barrier layers and methods for fabricating capacitors and other devices containing such barrier layers in order to protect cell dielectrics, such as Ta2O5, SrTiO3 (xe2x80x9cSTxe2x80x9d), (Ba,Sr)TiO3 (xe2x80x9cBSTxe2x80x9d), Pb(Z,Ti)O3 (xe2x80x9cPZTxe2x80x9d), SrBi2Ta2O9 (xe2x80x9cSBTxe2x80x9d) and Ba(Zr,Ti)O3 (xe2x80x9cBZTxe2x80x9d), against dielectric degradation through thermal effects and interaction with surrounding materials.
The chemical vapor deposited Ptxe2x80x94Rh co-deposited alloy layers of the invention provide excellent barrier protection, conductivity as capacitor electrodes, and conformality, and so may be employed either as capacitor electrodes, or as separate barrier layers formed adjacent to conventional capacitor electrodes, either atop these electrodes or interposed between the electrode and the capacitor dielectric. Preferably, the CVD Ptxe2x80x94Rh alloy layer according to the invention comprises a thin barrier layer between a cell dielectric and an underlying polysilicon (poly) plug or drain in a DRAM cell array, as well as acting as a lower electrode. The term xe2x80x9cCVD platinum-rhodium alloyxe2x80x9d herein means a material layer containing platinum and rhodium in the compositional ranges and having the characteristic high degree of conformality described herein.
The present invention also provides a co-deposition method for forming CVD Ptxe2x80x94Rh barrier films using a platinum precursor composition, a rhodium precursor composition, and reaction gases for causing chemical vapor co-deposition of a Ptxe2x80x94Rh alloy in a CVD reactor.